Implementation of scheduling schemes using a sequencer circuit

Massoud R. Hashemi, Alberto Leon-Garcia
Implementation of scheduling schemes using a sequencer circuit
Pages: 308-317
Broadband Networking Technologies, Dallas, TX, USA, 2 November 1997. SPIE Proceedings 3233 SPIE 1997

Abstract:
The implementation of different well-known scheduling schemes using a cell sequencer/scheduler circuit, already proposed by the authors, is investigated. Two groups of scheduling schemes, namely priority-based and rate-based schemes are considered. The first group includes static and dynamic priority schemes such as head-of-line priority and windowed priority schemes. The second group includes fair queueing, self-clocked fair queueing, and pacing mechanisms. The application of the sequencer in shaping and policing circuits in ATM networks is also addressed. A mechanism of scheduling real-time and non-real-time traffics using two different algorithms but a common sequencer is also presented to demonstrate the capability of the sequencer to implement a combination of algorithms and functions in the same environment.

November, 1997

Link To Online Resource: 

http://spie.org/x648.html?product_id=275459&origin_id=x648