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A RAM-Based Generic Packet Switch with Scheduling Capability
Authors
Massoud R Hashemi, Alberto Leon-Garcia
Publication date
1997/12/2
Conference
1997 2nd IEEE International Workshop on Broadband Switching Systems Proceedings, IEEE BSS'97. Workshop Theme'Switching Systems for the Broadband Internet and for QoS on Demand'(Cat. No. 97TH8352)
Pages
155-163
Publisher
IEEE
Description
A generic hardware solution is introduced for switching variable-length packets. The switch can be used in a multiprotocol environment including IP and ATM protocols. In this architecture the packets and/or cells are stored in a shared RAM memory as the main storage resource in the switch, and similar to RAM-based, shared-buffer ATM switch, for each packet a fixed-length minicell is given to a queue controller which provides queueing and scheduling. A bank of sequencer circuits can be used as the controller. We introduce a new version of the single-queue switch, as a compact controller to replace the bank of sequencers with a single sequencer, with the same speed and size. Fair queueing scheduling is implemented by the controller. Other schemes can also be implemented using the sequencer circuit, such as priority queueing. Plug-in modules handle the link and network (routing) protocols. Therefore, these …